1. Field of the Invention
The present disclosure relates to methods of fabricating semiconductor devices, and more particularly, to methods of fabricating semiconductor devices including PMOS devices having embedded SiGe (eSiGe) in a substrate.
2. Description of the Related Art
In order to meet the demand of users for low profile electronics, in enhanced Very Large Scale Integration (VLSI) processes, stress engineering has been used to improve performance of devices. One of the effective ways is to utilize embedded SiGe (eSiGe) structures to increase hole mobility in the channel regions of a PMOS device.
In a Sigma-shaped (Σ-shaped) eSiGe structure, stress in the channel regions can be effectively increased since the lattice constant of SiGe is larger than that of Si and the distance between source and drain regions is reduced by using the Σ-shaped SiGe structure.
A prior art method of forming a Σ-shaped SiGe structure in a PMOS device is shown in FIGS. 1A to 1D. After forming on a Si substrate a dielectric layer, gates are formed on the dielectric layer and sidewall spacers are formed on opposite sides of each gate (FIG. 1A). Thereafter, a recess is formed between adjacent gates in the Si substrate by dry etching, as shown in FIG. 1B. The cross section of the recess shown in FIG. 1B has a substantially rectangular shape with a planar bottom and vertical walls, which is defined by four vertices A, B, C and D.
Next, as shown in FIG. 1C, the rectangular-shaped recess is wet etched in an orientation selective manner to be expanded into a Σ-shaped recess. Commonly, orientation selective wet etching has a faster etch rate on (100) orientation of planes than on (111) orientation of planes. In fact, orientation selective wet etching substantially stops on (111) orientation of planes. As a result, two vertices C, D formed after the dry etching shown in FIG. 1B are remained as etching stop points of (111) orientation of planes. Finally, as shown in FIG. 1D, SiGe is epitaxially grown in the resulting Σ-shaped recess to form SiGe source and drain regions.
After having thoroughly studied the prior art methods of forming Σ-shaped SiGe, the inventors of the present invention discovered that it was difficult to obtain an epitaxial growth of SiGe using the prior art methods.
Specifically, in the dry etching process performed on the substrate shown in FIG. 1B, defects such as Si lattice mismatch or the like can occur at edges of the formed rectangular-shaped recess, particularly at the vertices C, D shown in FIG. 1B, due to plasma bombardment. As mentioned above, as a result of orientation selective wet etching, the vertices C, D will keep out of etching as (111) orientation etching stop points. In the subsequent epitaxial growth of SiGe, the seed layer is very sensitive to Si surface conditions, such as cleanness and Si lattice condition. Defects such as Si lattice mismatch can lead to the difficulty in the epitaxial growth of a seed layer. Hence, as shown in FIG. 1E, Si lattice defects at points of C and D will make the implementation of subsequent epitaxial growth of a SiGe seed layer more difficult.